The present invention relates to a semiconductor integrated circuit device, and to a technique for laying out devices and interconnections employed in a dynamic RAM (Random Access Memory) wherein peripheral circuits comprised of random logic CIRCUITS and bonding pads are placed in a central portion of a semiconductor chip, for example.
An example of a dynamic RAM wherein bonding pads and their corresponding peripheral circuits are disposed in a central portion of a semiconductor chip is disclosed in U.S. Pat. No. 5,602,771 (Feb. 11, 1997). In the dynamic RAM disclosed in this patent, areas which constitute the peripheral circuits are provided crosswise in vertical and horizontal central portions of a memory chip. Memory arrays are laid out in areas divided into four parts by the cross-shaped areas.